View HN58V256AI_2081602.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HN58V256AI series 256k eeprom (32-kword 8-bit) wide temperature range version ade-203-616c (z) rev. 3.0 oct. 24, 1997 description the hitachi hn58v256a is electrically erasable and programmable rom organized as 32768-word 8- bit. it has realized high speed low power consumption and high reliability by employing advanced mnos memory technology and cmos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features single 3 v supply: 2.7 to 5.5 access time: 120 ns max power dissipation: ? active: 20 mw/mhz, (typ) ? standby: 110 m w (max) on-chip latches: address, data, ce , oe , we automatic byte write: 10 ms max automatic page write (64 bytes): 10 ms max data polling and toggle bit data protection circuit on power on/off conforms to jedec byte-wide standard reliable cmos with mnos cell technology 10 5 erase/write cycles (in page mode) 10 years data retention software data protection operating temperature range: C40 to 85 c
HN58V256AI series 2 ordering information type no. access time package hn58v256afpi-12 120 ns 400 mil 28-pin plastic sop (fp-28d) hn58v256ati-12 120 ns 28-pin plastic tsop (tfp-28db) pin arrangement hn58v256afpi series hn58v256ati series (top view) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 oe 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HN58V256AI series 3 pin description pin name function a0 to a14 address input i/o0 to i/o7 data input/output oe output enable ce chip enable we write enable v cc power supply v ss ground block diagram v v oe ce a5 a0 a6 a14 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch to to to
HN58V256AI series 4 operation table operation ce oe we i/o read v il v il v ih dout standby v ih * 2 high-z write v il v ih v il din deselect v il v ih v ih high-z write inhibit v ih v il data polling v il v il v ih dout (i/o7) notes: 1. refer to the recommended dc operating condition. 2. : dont care absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc C0.6 to +7.0 v input voltage relative to v ss vin C0.5* 1 to +7.0* 3 v operating temperature range* 2 topr C40 to +85 c storage temperature range tstg C55 to +125 c notes: 1. vin min = C3.0 v for pulse width 50 ns 2. including electrical characteristics and data retention 3. should not exceed v cc + 1 v.
HN58V256AI series 5 recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 2.7 3.0 5.5 v v ss 00 0v input voltage v il C0.3* 1 0.6 v v ih 2.4* 3 v cc + 0.3* 2 v operating temperature topr C40 85 c notes: 1. v il min: C1.0 v for pulse width 50 ns. 2. v ih max: v cc + 1.0 v for pulse width 50 ns. 3. v ih min: 3.0 v at v cc = 3.6 to 5.5v dc characteristics (ta = C40 to +85 c, v cc = 2.7 to 5.5 v) parameter symbol min typ max unit test conditions input leakage current i li 2 m av cc = 5.5 v, vin = 5.5 v output leakage current i lo 2 m av cc = 5.5 v, vout = 5.5/0.4 v v cc current (standby) i cc1 20 m a ce = v cc i cc2 1 ma ce = v ih v cc current (active) i cc3 8 ma iout = 0 ma, duty = 100%, cycle = 1 m s at v cc = 3.6 v 12 ma iout = 0 ma, duty = 100%, cycle = 1 m s at v cc = 5.5 v 15 ma iout = 0 ma, duty = 100%, cycle = 120 ns at v cc = 3.6 v 30 ma iout = 0 ma, duty = 100%, cycle = 120 ns at v cc = 5.5 v output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh v cc 0.8 v i oh = C400 m a capacitance (ta = 25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 6 pf vin = 0 v output capacitance* 1 cout 12 pf vout = 0 v note: 1. this parameter is periodically sampled and not 100% tested.
HN58V256AI series 6 ac characteristics (ta = C 40 to + 85 c, v cc = 2.7 to 5.5 v) test conditions input pulse levels: 0.4 v to 2.4 v (v cc 3.6v), 0.4v to 3.0 v (v cc > 3.6 v) input rise and fall time: 5 ns input timing reference levels: 0.8, 1.8 v output load: 1ttl gate +100 pf output reference levels: 1.5 v, 1.5 v read cycle HN58V256AI -12 parameter symbol min max unit test conditions address to output delay t acc 120 ns ce = oe = v il , we = v ih ce to output delay t ce 120 ns oe = v il , we = v ih oe to output delay t oe 10 60 ns ce = v il , we = v ih address to output hold t oh 0ns ce = oe = v il , we = v ih oe ( ce ) high to output float* 1 t df 040ns ce = v il , we = v ih
HN58V256AI series 7 write cycle parameter symbol min * 2 typ max unit test conditions address setup time t as 0 ns address hold time t ah 50ns ce to write setup time ( we controlled) t cs 0 ns ce hold time ( we controlled) t ch 0 ns we to write setup time ( ce controlled) t ws 0 ns we hold time ( ce controlled) t wh 0 ns oe to write setup time t oes 0 ns oe hold time t oeh 0 ns data setup time t ds 70ns data hold time t dh 0 ns we pulse width ( we controlled) t wp 200 ns ce pulse width ( ce controlled) t cw 200 ns data latch time t dl 100 ns byte load cycle t blc 0.3 30 m s byte load window t bl 100 m s write cycle time t wc 10* 3 ms write start time t dw 0* 4 ns notes: 1. t df is defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. use this device in longer cycle than this value. 3. t wc must be longer than this value unless polling techniques is used. this device automatically completes the internal write operation within this value. 4. next read or write operation can be initiated after t dw if polling techniques is used. 5. a16 through a14 are page addresses and these addresses are latched at the first falling edge of we . 6. a16 through a14 are page addresses and these addresses are latched at the first falling edge of ce . 7. see ac read characteristics.
HN58V256AI series 8 timing waveforms read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df
HN58V256AI series 9 byte write timing waveform (1) ( we controlled) address ce we oe din t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh byte write timing waveform (2) ( ce controlled) address ce we oe din t wc t ah t ws t as t oeh t wh t oes t ds t dh t cw t bl
HN58V256AI series 10 page write timing waveform (1) ( we controlled) address a0 to a14 we ce oe din t as t ah t bl t wc t oeh t dh t oes t ch t cs t wp t dl t blc t ds *5 page write timing waveform (2) ( ce controlled) address a0 to a14 we ce oe din t as t ah t bl t wc t oeh t dh t oes t wh t ws t cw t dl t blc t ds *6
HN58V256AI series 11 data polling timing waveform t ce t oeh t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x *7 *7 an
HN58V256AI series 12 toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from 1 to 0 (toggling) for each read. when the internal programming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 beginning state is 1. 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh *1 *2 *2 address *3 *3 *4 din
HN58V256AI series 13 software data protection timing waveform (1) (in protection mode) v ce we address data 5555 aa 2aaa 55 5555 a0 t blc t wc cc write address write data software data protection timing waveform (2) (in non-protection mode) v ce we address data t wc cc normal active mode 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 20
HN58V256AI series 14 functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 m s from the preceding falling edge of we or ce . when ce or we is high for 100 m s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data polling data polling indicates the status that the eeprom is in a write cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs from i/o7 to indicate that the eeprom is performing a write operation. we , ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce , and data is latched by the rising edge of we or ce . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles.
HN58V256AI series 15 data protection 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. to prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less. be careful not to allow noise of a width of more than 20 ns on the control pins. we ce oe v 0 v v 0 v 20 ns max ih ih 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom should be kept in unprogrammable state during v cc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * *
HN58V256AI series 16 (1) protection by ce , oe , we to realize the unprogrammable state, the input level of control pins must be held as shown in the table below. ce v cc oe v ss we v cc : dont care. v cc : pull-up to v cc level. v ss : pull-down to v ss level. 3. software data protection to prevent unintentional programming, this device has the software data protection (sdp) mode. the sdp is enabled by inputting the following 3 bytes code and write data. sdp is not enabled if only the 3 bytes code is input. to program data in the sdp enable mode, 3 bytes code must be input before write data. data aa 55 a0 write data } address 5555 2aaa 5555 write address normal data input the sdp mode is disabled by inputting the following 6 bytes code. note that, if data is input in the sdp disable cycle, data can not be written. data aa 55 80 aa 55 20 address 5555 2aaa 5555 5555 2aaa 5555 the software data protection is not enabled at the shipment. note: there are some differences between hitachis and other companys for enable/disable sequence of software data protection. if there are any questions , please contact with hitachi sales offices.
HN58V256AI series 17 package dimensions hn58v256afpi series (fp-28d) 0 ?8 0.17 0.05 1.0 0.2 0.20 0.10 2.50 max 8.4 18.3 18.8 max 1.12 max 28 15 1 14 11.8 0.3 1.7 0.20 0.15 m 1.27 0.40 0.08 0.38 0.06 0.15 0.04 hitachi code jedec eiaj weight (reference value) fp-28d conforms ? 0.7 g unit: mm dimension including the plating thickness base material dimension
HN58V256AI series 18 package dimensions (cont.) hn58v256ati series (tfp-28db) 0.10 m 0.55 8.00 0.22 0.08 13.40 0.30 0.17 0.05 0.13 1.20 max 11.80 0 ?5 28 1 14 15 8.20 max 0.10 +0.07 ?.08 0.50 0.10 0.80 0.45 max hitachi code jedec eiaj weight (reference value) tfp-28db ? ? 0.23 g 0.20 0.06 0.15 0.04 unit: mm dimension including the plating thickness base material dimension
HN58V256AI series 19 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
HN58V256AI series 20 revision record rev. date contents of modification drawn by approved by 1.0 jul. 9, 1996 initial issue y. nagai t. wada 2.0 mar. 18, 1997 recommended dc operating conditions v ih (min): 3.0 v to 2.4 v functional description data protection 3: addition of note data protection 3: change figures of software data protection y. nagai k. furusawa 3.0 oct. 24, 1997 timing waveforms read timing waveform: correct error

▲Up To Search▲

Price & Availability of HN58V256AI

	To Download HN58V256AI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .